1. Field of the Invention
The present invention relates to a film formation method and apparatus for a semiconductor process, which are used for forming a film on a target substrate, such as a semiconductor wafer. The term “semiconductor process” used herein includes various kinds of processes which are performed to manufacture a semiconductor device or a structure having wiring layers, electrodes, and the like to be connected to a semiconductor device, on a target substrate, such as a semiconductor wafer or a glass substrate used for an LCD (Liquid Crystal Display) or FPD (Flat Panel Display), by forming semiconductor layers, insulating layers, and conductive layers in predetermined patterns on the target substrate.
2. Description of the Related Art
Conventionally, a poly-silicon film (poly-crystalline silicon film) is widely used for gate electrodes of MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistor). In a MOSFET, a gate electrode is disposed through a gate insulating film on a channel region defined between a pair of source/drain regions. The gate electrode is used to control electric current flowing through the channel region between the source/drain regions.
In general, where a poly-silicon film is used as the gate electrode, it is deposited on the gate insulating film by CVD (Chemical Vapor Deposition). For example, mono-silane (SiH4) gas is supplied as a process gas into a process field within the reaction container in which a wafer is placed. The process gas is thermally decomposed in the process field set at a temperature for poly-crystallizing silicon. As a consequence, a poly-silicon film consisting of an agglomeration of micro-crystalline grains is formed on the gate insulating film. The grain size of micro-crystalline grains can be controlled by the temperature, pressure, gas type, flow rate, etc. used in CVD.
Where a poly-silicon film is used as the gate electrode, it is doped with a carrier impurity element to be conductive. Typically, the gate electrode is doped to be of the same conductivity type as the source/drain regions. Accordingly, in the case of a P-channel MOSFET, P-source/drain regions and a P-gate electrode are formed in and on the N-silicon substrate. They are doped with a P-impurity element, such as boron (B).
Ion implantation methods are utilized to perform doping of carrier impurity elements. For example, boron used as a carrier impurity element is ionized, and accelerated by an electric field. The boron thus accelerated is selected from charged species by a mass spectroscope using a magnetic field, and further accelerated by an electric field toward a target object. At this time, the implantation energy is adjusted to control the boron implantation depth in the thickness direction of a poly-silicon film. In general, the wafer W is then subjected to a heat process to thermally diffuse the ion-implanted boron.
In recent years, in line with the general reduction in film thickness of semiconductor devices, the thickness of poly-silicon films used as gate electrodes has been reduced to around 0.1 μm. Where a thin poly-silicon film is used, boron may penetrate through the poly-silicon film during ion implantation of the boron. If boron reaches the gate insulating film or channel region below the poly-silicon film, it deteriorates the electrical properties of the device. Conversely, if the ion implantation energy of boron is insufficient, the boron is reflected off the surface of the poly-silicon film and thus is not implanted. Accordingly, there is a certain lower limit to the implantation energy.